Senior Design Verification Engineer

🚀 Senior Verification Engineer – We’re Hiring!

Looking for an experienced Verification Engineer to join a highly skilled and dynamic engineering team.

🔹 5+ years of hands-on Verification experience

🔹 Strong expertise in SystemVerilog & UVM

🔹 Experience with FPGA / ASIC Verification

🔹 Block-level to Full-chip Verification

🔹 Test Plan, Coverage & RTL Debugging

🔹 Experience working closely with FPGA, System & Algorithm teams

🔹 Python / TCL / Bash scripting and Linux experience

If you’re passionate about digital verification and enjoy working on complex, cutting-edge technologies — let’s talk!

📩 Feel free to reach out or tag someone who might be a great fit. [email protected]