Senior Design Verification Engineer

This is a full-time on-site role for a Senior Design Verification Engineer located in Hyderabad. The Design Verification Engineer will be responsible for performing Functional verification. Key tasks include debugging, ensuring designs meet customer requirements, documenting verification plans, and collaborating with cross-functional teams to improve the verification process.

Responsibilities

• Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.
• Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Come up tests and verification infrastructure for complex IPs/sub-systems by using the test plan document.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Perform functional coverage driven verification closure.
• Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Qualifications

• B.Tech. with 1-3 years/ M.Tech. with 0-2 years of relevant experience.
• Experience in verification flow understanding of complex IPs/units and sub-systems.
• Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
• Expertise in Verilog.
• Knowledge in System Verilog or similar HVL.
• Familiarity with verification methodologies like UVM and exposure to industry standard verification tools for simulation and debug.
• Experience with System Verilog Assertion (SVA) a plus.
• Experience with Perl, Python or other scripting language is a plus
• Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus