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Senior Design Verification Engineer

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Onsite

Senior Design Verification Engineer

Amazon

Senior Design Verification Engineer

Skills

MATLABAI

2 months ago

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Important information


Salary:

$159,200 – $247,600 / year

Location:

Austin, TX, USA

Work mode:

Onsite

Published on:

10 September 2026

What they need


Who you are

  • Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering
  • 3+ years of UVM, C, System C, and scripting experience
  • 7+ years in verification preferably in communication systems
  • Master's or Ph.D degree in Electrical / Communications Engineering
  • 10+ years in digital verification, preferably in communication systems
  • Proficiency in leveraging AI/LLM tools to accelerate verification workflows including AI-assisted test plan, test case generation, debug, human in loop coverage sign off review
  • Familiarity with Matlab
  • Modem design verification experience
  • System C or Matlab model : development or DV integration experience
  • Familiarity with formal verification techniques
  • Strong written and verbal skills

What the job involves

  • Be part of Amazon Leo’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways
  • This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies
  • Implement a state of the art verification environment for IP, subsystem and SOC to facilitate testing of the DUT against reference models
  • Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
  • Understand and debug system level communication scenarios on pre silicon and post silicon environments
  • Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C
  • Develop a highly automated environment to triage regression fails and report issues to stake holders

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