Senior Design Verification Engineer

Key Responsibilities

Testbench Development: Architect, develop, and maintain advanced constrained-random testbenches from scratch using SystemVerilog and UVM architectures.

IP & Subsystem Verification: Drive the full verification lifecycle for high-performance PCIe and CXL controller IPs and subsystems.

Test Planning & Execution: Define detailed verification plans based on functional specifications, execute tests, and close functional and code coverage.

Debugging: Debug complex design, testbench, and protocol-level issues efficiently using industry-standard tools and waveform viewers.

Collaboration: Partner closely with architecture, design, and firmware teams to resolve hardware bugs and clarify specification ambiguities.

Required Skills & Qualifications

Protocol Expertise: In-depth, hands-on understanding of PCIe (Gen 4/5/6) and CXL (1.1/2.0/3.0+) protocols, including sub-protocols like cxl.io, cxl.cache, and cxl.mem.

Methodology Mastery: Strong, proven expertise in UVM testbench development with hands-on experience building scalable, reusable verification environments.

Language Proficiency: Expert knowledge of SystemVerilog, SystemVerilog Assertions (SVA), and functional coverage coding.

Problem Solving: Excellent analytical, problem-solving, and debugging skills under tight timelines.

Soft Skills: Ability to ramp up quickly on complex architectures, self-motivate, and collaborate effectively across global engineering teams.

Preferred Qualifications

Experience with formal verification techniques or gate-level simulations (GLS).

Familiarity with hardware description languages (Verilog/VHDL) to assist in design code reviews.

Knowledge of scripting languages (Python, Perl, or Tcl) for automated regression testing.Role & responsibilities

Preferred candidate profile