E
Einfochips
Senior Design Verification Engineer
Skills
Python
1 month ago
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Important information
Contract type:
Permanent
Location:
Bengaluru, Karnataka, India
Work mode:
Onsite
Published on:
28 September 2026
What they need
- 4 - 8 years of experience in ASIC/SoC/IP Design Verification.
- Strong hands-on expertise in SystemVerilog and UVM.
- Good understanding of Ethernet MAC architecture and functionality.
- Good understanding of Ethernet PHY / PCS (Physical Coding Sublayer).
- Familiarity with Ethernet standards and concepts such as MAC/PCS datapath, packet framing, encoding/decoding, link establishment, and error handling.
- Strong experience in developing UVM testbenches, sequences, drivers, monitors, scoreboards, and functional coverage.
- Good understanding of constrained-random verification and coverage-driven verification.
- Experience with debugging simulation failures and waveform analysis.
- Good knowledge of RTL design concepts, digital logic, and common on-chip interfaces.
- Experience with coverage analysis and closure, including functional and code coverage.
- Good scripting/debugging skills using Python, Perl, Tcl, or similar is a plus.
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