Senior Design Verification Engineer

• Define DV strategy and metrics, leading test plan creation and benchmark definitions from specs to emulation levels
• Architect, maintain, and enhance UVM/OVM testbenches across block and full chip levels
• Drive coverage closure: code & functional coverage, assertion validation, power aware UPF/CPF tests
• Automate regression flows, debug regressions using waveform tools, and debug RTL Mentor and lead a verification team, manage DV execution, and escalate issues to maintain schedule
• Support tool agnostic EDA ecosystem, including simulation (e.g., NCVerilog), lint tools, emulation platforms, and debug environments
• Collaborate with architects and design owners to interpret specs, create use case scenarios, and influence feature verifiability

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