Senior Design Verification Engineer

Required Skills

5+ years of hands-on DV experience

Strong fluency in SystemVerilog, UVM, and Verilog

Solid working knowledge of JTAG and APB protocols

Good analytical/debugging skills — able to root-cause complex simulation and RTL/testbench issues independently

Nice to Have

Awareness of ATE testing methodology and flows (not mandatory, but a plus)

Familiarity with other bus/interface protocols (e.g., AXI, I2C, SPI, AHB) — added advantage

Basic understanding of DFT concepts (scan, BIST, boundary scan, ATPG) — added advantage