Senior Design Verification Engineer

We are seeking a highly skilled Senior Design Verification Engineer to join our team in Karnataka. The ideal candidate will have extensive experience in design verification methodologies and tools, particularly in UVM, SystemVerilog, and Verilog. This role is critical in ensuring the quality and functionality of our complex SoC designs through rigorous verification processes. Key Responsibilities: - Develop and implement verification plans for SoC designs, ensuring comprehensive coverage of all functional aspects. - Utilize UVM and SystemVerilog to create testbenches and verification environments that facilitate thorough testing of RTL designs. - Collaborate with design engineers to understand design specifications and translate them into effective verification strategies. - Perform RTL verification and emulation using tools such as ZeBu and Palladium, ensuring that designs meet performance and functional requirements. - Conduct thorough debugging and analysis of simulation results, identifying and resolving issues in a timely manner. - Mentor junior engineers and provide guidance on best practices in design verification. - Stay updated with the latest trends and advancements in verification methodologies and tools to continuously improve the verification process. Required Skills: - Strong expertise in UVM, SystemVerilog, and Verilog. - Experience with emulation tools like ZeBu and Palladium. - Proficient in SoC and RTL verification methodologies. - Familiarity with ARM architecture and transactor-based verification. - Excellent problem-solving skills and attention to detail. - Strong communication and teamwork abilities. If you are passionate about design verification and are looking for a challenging role in a dynamic environment, we encourage you to apply. Join us in shaping the future of technology through innovative verification solutions.

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