Senior Design Verification Engineer

About the Role

We are seeking experienced Design Verification professionals to drive verification of complex IPs, subsystems, and SoCs. The ideal candidate will have strong expertise in SystemVerilog/UVM-based verification methodologies and a proven track record of delivering high-quality silicon.

Key Responsibilities

• Lead verification activities for IP, Subsystem, and SoC-level designs.
• Develop and execute comprehensive verification plans.
• Build and enhance UVM/SystemVerilog verification environments.
• Develop testcases, assertions, checkers, and coverage models.
• Drive functional, code, and assertion coverage closure.
• Debug complex design and verification issues.
• Collaborate closely with architecture, design, validation, and software teams.
• Mentor junior engineers and provide technical leadership across projects.

Required Skills & Experience

• 8+ years of experience in Design Verification.
• Strong hands-on experience in SystemVerilog and UVM.
• Expertise in IP, Subsystem, and/or SoC Verification.
• Experience in verification planning, coverage-driven verification, and debug.
• Strong understanding of industry-standard verification methodologies.
• Experience with scripting languages such as Python, Perl, or Shell is an added advantage.

Preferred Domain Experience

Candidates should have strong experience in one or more of the following areas:

• Ethernet IPs – IP, Subsystem, or SoC Verification
• XPU Chassis – SoC/Subsystem Verification
• cHBM Base Die – Subsystem or SoC Verification
• SerDes – Subsystem or SoC Verification