Senior Dft Engineer

We are looking for an experienced Design-for-Test (DFT) Engineer with 10+ years of industry experience to join our semiconductor design team. The ideal candidate will have strong hands-on expertise in DFT architecture, implementation, verification, and sign-off for complex SoC designs.

Key Responsibilities

• Define and implement DFT architecture for complex SoC designs.
• Perform Scan Insertion, Scan Compression, MBIST, and boundary scan implementation.
• Develop and execute ATPG patterns and analyze test coverage.
• Perform DFT validation using RTL simulation and Gate-Level Simulation (GLS).
• Debug DFT-related issues during simulation, synthesis, and post-layout stages.
• Work closely with RTL, Verification, Physical Design, and PnR teams to ensure DFT requirements are met.
• Collaborate with PnR teams for DFT timing closure, test mode constraints, and design closure.
• Drive DFT sign-off activities including test coverage, simulation validation, and pattern verification.
• Support silicon bring-up, production test, and failure analysis activities when required.
• Mentor junior engineers and contribute to DFT methodology improvements.

Required Skills

• 10+ years of experience in DFT design and implementation.
• Strong expertise in MBIST, Scan Insertion, Scan Compression, ATPG, and DFT Validation.
• Hands-on experience with RTL simulation and Gate-Level Simulation (GLS).
• Experience in DFT architecture and implementation for complex SoCs.
• Strong understanding of testability concepts, fault models, and test coverage analysis.
• Experience working with PnR teams for test timing closure and DFT constraints.
• Good debugging skills across RTL, netlist, and post-layout stages.
• Experience with industry-standard DFT tools such as Synopsys TestMAX / DFT Compiler / TetraMAX, Siemens Tessent, Cadence Modus, or equivalent.
• Good understanding of Verilog/SystemVerilog and scripting languages such as Tcl, Perl, or Python.
• Strong communication and stakeholder-management skills.

Preferred Skills

• Experience in LBIST, IJTAG, JTAG, boundary scan, or memory repair.
• Experience in low-power DFT and multi-voltage domain designs.
• Exposure to silicon bring-up and ATE pattern generation.
• Experience in advanced technology nodes and high-complexity SoC programs.

Education

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related discipline.