Senior Engineer - Analog Layout

Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions to global customers. The company has deep expertise across the semiconductor value chain, enabling clients to build next-generation products with high performance, quality, and faster time-to-market. Its engineering team covers the full design spectrum, from Analog Circuit Design and Custom Layout to RTL, Verification, Physical Design, Embedded Design, and full-chip/SoC backend. SiMaxTech works across a wide range of process technologies, from mature nodes like 65nm and 40nm to advanced nodes such as 7nm, 5nm, 3nm, and emerging nodes including 2nm and 18A. With a culture of continuous learning, innovation, and customer-centric delivery, the company aims to be the preferred semiconductor design partner for global customers.

Role Description The Senior Engineer – Analog Layout will be responsible for designing, implementing, and optimizing analog layout for complex integrated circuits, with a focus on high-performance and reliable power management and analog blocks. This full-time, on-site role is based in Bengaluru South and involves close collaboration with analog circuit designers to translate schematics into robust layouts that meet performance, area, and reliability targets. Day-to-day tasks include creating device-level and block-level layouts, performing layout-versus-schematic (LVS) and design rule checks (DRC), ensuring matching and noise performance, and addressing electromigration and IR-drop concerns. The role also includes working across different technology nodes, preparing documentation, participating in design reviews, and coordinating with cross-functional teams to support tape-out and post-silicon improvements.

Qualifications

• Strong foundation in analog domain, including Analog, Analog Circuits, and Analog Circuit Design skills.
• Proficiency in Circuit Design and Power Management for integrated circuits.
• Solid experience in analog/custom layout tools and flows (e.g., Cadence Virtuoso or equivalent), including DRC/LVS and parasitic extraction.
• Understanding of semiconductor process technologies across multiple nodes (e.g., 65nm and below), device physics, matching, and layout-dependent effects.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, with substantial experience in analog layout design.
• Ability to work on-site in Bengaluru South, collaborate effectively with multidisciplinary teams, and communicate clearly in written and spoken English.
• Experience with mixed-signal designs, ESD and reliability considerations, and prior tape-out experience is highly beneficial.