Senior Engineer II-Validation

The project involves validating all the features and interfaces supported on the FPGA by creating and using validation designs that are partitioned into RTL and Embedded Processor Application. Test and debug the silicon on board with the help of lab equipment and protocol testers. Typical day for Validation Engineer would include following activities:

• Validation design creation using Microchip’s FPGA design flow
• RTL and Embedded C based test design development
• Validation of all features of FPGA
• Debug and root cause analysis, validating workaround and fixes
• Study of specification and validation plans
• Board schematic verification
• Create and maintain required hardware setup, bring up the silicon and validate use cases capture results
• Documentation of test results, reviewing with stakeholder and getting sign-off
• Providing regular detailed status reports, presenting status in dept meetings, follow through on action items. Attend deep dive and debug discussions with teams in the US.
• Develop automation and regression design and flow
• File Bugzilla/jira tickets during the design creation and validation phase, perform the experiments required to isolate and root cause, validate workaround/fixes and ensure closure during sign-off

Requirements/Qualifications:

• Strong hands-on FPGA Silicon validation experience
• Experience working on JESD204B & JESD204C interfaces, bringup and performing interoperability test
• Hands-on validation experience in one or many of the below protocols will be a plus
• PCIe Gen4/5
• DDR 4/5
• 100G/50G/40G/25G/10G Ethernet
• USB 3.2
• 1588 PTP
• MIPI
• MACSEC
• Working knowledge of SERDES CTLE and DFE circuits preferred
• Good knowledge of embedded processors and peripherals such as SPI, I3C, UART, NOC, Trace and USB. Hands-on experience in ‘C’ programming, debugging test application.
• Responsible for developing testbenches and verifying validation designs
• Responsible for handling complex use cases on above protocols at block level and subsystem level
• Excellent verbal and written communication skills in English
• Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal)
• Strong commitment to quality and customer satisfaction
• Excellent verbal and written communication skills in English
• BE/BTech or ME/MTech with 6+ yrs of relevant work experience

Travel Time:

0% - 25%

Pay: ₹1,500,000.00 - ₹3,500,000.00 per year

Work Location: In person