Senior Engineer II - Verification Engineer

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Job Description:

About the Role

We are seeking an experienced C-Based FPGA Pre-Silicon Verification Engineer to drive verification activities for next-generation FPGA platform. In this role, you will develop and execute verification strategies for FPGA verification. You will work closely with RTL designers, architects, firmware teams, and validation engineers to ensure robust functional coverage and early bug detection across complex FPGA designs.

The role involves developing C/C++ based test frameworks, firmware-driven verification environments, simulation based verification flows, and hardware/software co-verification methodologies. You will contribute to pre-silicon verification using SystemVerilog/UVM environments while leveraging embedded software, BFMs, and protocol stacks to validate real-world use cases.

You will independently manage complex verification tasks, debug RTL and firmware interactions, analyze failures, and drive verification closure. The ideal candidate will have strong expertise in FPGA/SoC architectures, embedded software development, and pre-silicon verification methodologies.

This role also includes mentoring engineers, defining best practices, and contributing to innovation and continuous improvement in verification methodologies and automation flows.

Requirements/Qualifications:

Qualifications

Bachelor’s or Master’s degree in Electrical Engineering or a related field.

Required Skills and Experience

• 8+ years of experience in FPGA/ASIC functional verification with strong focus on C-based or embedded software-driven pre-silicon verification..
• Experience with RISC-V, ARM-based SoCs, or embedded CPU verification
• Hands-on experience developing C/C++ testcases and verification frameworks for FPGA/SoC verification
• Strong understanding of FPGA architectures, SoC subsystems, memory architectures, interrupts, DMA, boot flows, and embedded processors
• Strong scripting skills in Python, Shell, Perl, and TCL.
• Experience with coverage-driven and assertion-based verification methodologies.
• Experience developing constrained-random and directed simulation testcases using System Verilog/UVM; knowledge of C-based testcase development is a plus.
• Solid understanding of IC chip design, development flows, and verification methodologies.
• Proven ability to develop verification plans, build robust UVM testbenches, define functional coverage models, execute regressions, analyze coverage gaps, and drive closure against verification goals.
• Strong analytical, debugging, and problem-solving skills.

Excellent written and verbal communication skills in English

Travel Time:

No Travel

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