Senior Engineer (Yield Enhancement)

About the role

To liaise with module engineers on yield performance analysis, drive defect reduction and yield improvement activities, and supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation.

Key responsibilities

• Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation
• Train and certify YE Associate Engineers on recipe creation and defect source knowledge
• Maintain and enhance internal SOP/OCAP and involve in internal/external audit
• Operate FIB/SEM/EDX for inline failure analysis
• Operate and create recipes in Brightfield, Darkfield and other defect inspection tools
• Perform partition analysis on defect source and detailed reports on issues
• Build and develop defect source land tool's defect source fingerprinting
• Track inline defect performance by layer/process tool/chamber on weekly basis
• Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities
• Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems

About you

• Masters or Bachelor Degree in Electrical / Electronics / Chemical / Material Science Engineering
• 2-8 years of relevant fab work experience in high volume manufacturing of electronics components in an MNC or front end wafer fab industry preferred
• Excellent interpersonal and communication skills with good leadership capability
• Team player
• Responsible and accountable for complying with and implementing environmental, health, safety and security (EHSS) system, policies, procedures and guidelines