Senior FEINT/STA Engineer

The Role

We are looking for a Front-End Integration Engineer with 3+ years of experience to join our team in Bayan Lepas, Penang. You will work across the front-end ASIC flow from RTL to netlist, covering synthesis, timing, design quality checks, and verification while collaborating with cross-functional teams to support a smooth transition to physical design.

Key Responsibilities

• Drive front-end chip implementation, from RTL through synthesis and netlist delivery for physical design.
• Develop, implement, and improve ASIC front-end design methodologies and flows.
• Perform RTL quality checks, including lint and clock-domain crossing (CDC) analysis.
• Execute logic synthesis, timing analysis, and timing constraint validation to achieve design requirements.
• Perform formal equivalence checking to ensure consistency between different design stages.
• Analyze and resolve issues related to RTL quality, timing, synthesis, and design constraints.
• Collaborate with RTL, physical design, and other engineering teams to ensure a smooth transition from RTL to physical implementation.
• Work with EDA vendors on tool evaluation, flow development, and technology-related issues.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, or any related field
• Experience with Verilog RTL design and has experience of large digital ASIC project.
• Familiarity with front-end EDA tools such as Fusion Compiler / Design Compiler, PrimeTime, Formality / Conformal, SpyGlass, or equivalent tools.
• Hands-on experience in RTL synthesis, lint, CDC, formal verification, or STA.
• Good understanding of timing constraints and Static Timing Analysis (STA).
• Proficiency in Unix/Linux environments and scripting languages such as Tcl, Perl, or Python.
• Strong planning, problem-solving, and execution skills, with the ability to deliver according to project milestones.