Senior FPGA Design Engineer

;The Senior FPGA Design Engineer is responsible for architecting, designing, verifying, and integrating FPGA-based subsystems that form the backbone of advanced wireless communication and signal processing platforms. The role requires hands-on technical expertise in RTL development, FPGA tool flows, and hardware validation, along with the ability to work collaboratively with system, hardware, and firmware teams.

; Key Responsibilities

• ; FPGA Design Development

• ;Translate system-level specifications and algorithmic models into synthesizable RTL architectures.

• ;Develop RTL modules in VHDL/Verilog for control logic, DSP blocks, and high-speed interfaces.

• ;Implement digital signal processing functions such as filtering, modulation/demodulation, channel coding/decoding (LDPC, Turbo, BCH, etc.).

• ;Create timing and I/O constraints for synthesis, place-and-route, and static timing analysis.

• ;Optimize design for timing, resource utilization, and power efficiency.

• ;Generate FPGA bitstreams and support board-level validation.

• ; Verification Validation

• ;Develop self-checking test benches and functional verification environments.

• ;Perform module-level and top-level simulations using ModelSim or XSIM.

• ;Debug simulation mismatches and post-synthesis timing violations.

• ;Support system integration and real-time testing on FPGA evaluation or custom boards (e.g., Zynq SoC, Artix/Kintex UltraScale).

• ; Process Documentation

• ;Follow internal FPGA design workflows which are aligned with ISO standards

• ;Maintain design documents: FPGA architecture, Design document, interface specifications, verification reports, timing summaries, and utilization logs.

• ;Participate in formal design reviews Input Review, Output Review, VV Review, and Change Review with review records maintained in MoMs.

• ;Ensure all design baselines are version-controlled using SVN or equivalent tools.

• ; Cross-Functional Collaboration

• ;Work closely with system engineers to interpret waveform and communication specifications into hardware-friendly requirements.

• ;Coordinate with hardware and firmware teams for FPGA-board integration and software interaction.

• ;Support test engineers during on-board bring-up and system-level validation.

• ; Mentoring Knowledge Sharing

• ;Guide junior engineers in coding practices, simulation, and debugging techniques.

• ;Contribute to internal FPGA knowledge base and reusable IP library development.

; Professional Skills:

• ;Strong RTL design skills using VHDL/Verilog

• ;Thorough understanding of Xilinx FPGA s

• ;Simulation and verification using;ModelSim/XSIM

• ;Hands-on experience with Xilinx Vivado, Intel Quartus, or equivalent FPGA toolchains.

• ;Hands on with;Zynq SoC;or;Zynq UltraScale+;platforms preferred

• ;Hands-on synthesis, place route, static timing analysis, and constraint management.

• ;Hands-on with AXI, DDR, Ethernet, UART, SPI, I2C, and other digital interfaces.

• ;Experience with Zynq SoCs (PS-PL integration) or FPGA-based signal processing systems.

• ;Familiarity with scripting (Tcl/Python/Shell) for simulation compilation automation

• ;Configuration/Version control tools like SVN

; Desired Attributes/ Softskills

• ;Strong analytical and debugging ability at simulation and on-board levels which leads to decision making.

• ;Attention to design quality, reusability, and adherence to coding guidelines.

• ;Commitment to documentation and process discipline.

• ;Ability to take ownership of module-level or subsystem-level FPGA delivery.

• ;Collaborative team player with a continuous improvement mindset.

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