Senior FPGA Design Engineer

What You'll Do

• Own the FPGA architecture for latency-critical trading paths: market data ingest, order entry, and host interface.
• Write and optimize production RTL, then drive it to timing closure on the latest AMD/Xilinx devices. Set RTL, verification, and resource-management standards for a growing FPGA team. Make build-vs-buy decisions on IP, and integrate or replace existing cores as needed.
• Work directly with trading, quant, and infrastructure teams to translate latency requirements into hardware.

Must Have

• 4+ years of FPGA development with deep hands-on RTL experience in Verilog/SystemVerilog.
• Ownership of shipped designs written from scratch in at least two of: network packet processing (PCS, MAC, UDP, TCP/IP), high-speed Ethernet, PCI Express, or memory interfaces.
• Proven timing closure on complex designs, with strong resource management and latency optimization skills.
• Fluency with Vivado, Vitis, ModelSim/Questa, or Xilinx Simulator. Solid modern C and Python for tooling, host-side integration, and automation. .