Senior Hardware Engineer (Validation & Signal Integrity Correlation)

• SambaNova Systems is redefining what’s possible in AI infrastructure—and the hardware that powers it has to be flawless. As a Senior Hardware Validation & SI Correlation Engineer, you will own the technical bridge between simulation and silicon, ensuring that every high-speed link, control bus, and power rail in our next-generation AI server systems performs without compromise
• This is a high-impact, highly visible role that blends deep Signal Integrity (SI) expertise with rigorous system-level hardware validation. You will work at the frontier of AI compute—validating PCIe Gen5/6, DDR5, and 112G/224G Ethernet interfaces on systems pushing the limits of what data center hardware can do. If you thrive in a fast-paced lab environment, love digging into root cause, and want your work to directly accelerate the future of AI, this role is built for you
• SI Modeling & Measurement Correlation
• Drive the correlation between pre- and post-layout SI simulations and physical lab measurements, closing the loop between theory and hardware reality
• Quantify simulation-vs-measurement gaps for PCIe Gen5/6, DDR5, and 112G/224G Ethernet using S-parameters, TDR, and eye diagram analysis
• Develop and refine EM models for PCB discontinuities, high-speed connectors, and vias using Ansys HFSS, Cadence Sigrity, or equivalent tools
• Investigate discrepancies caused by manufacturing tolerances, material properties (Dk/Df), or de-embedding inaccuracies and drive them to resolution
• System-Level Electrical Validation
• Lead validation of housekeeping and control buses—I2C, SPI, eSPI, UART, SMBus—ensuring protocol compliance and robust timing margins
• Validate complex power-on/off sequences and correlate VR control loop simulations with physical transient response and ripple measurements
• Ensure reliable operation of sideband signals, reset logic, and BMC hardware interfaces under intensive AI workloads
• Work cross-functionally with SI, Power Integrity (PI), and Firmware teams to resolve system-hang and link-training failures rooted in electrical noise or power instability
• Test Methodology & Automation
• Author comprehensive Hardware Validation Plans (HVP) with full coverage of critical electrical test points
• Build Python-based automation scripts to drive data collection from VNAs, BERTs, and oscilloscopes—accelerating validation throughput and repeatability

Benefits

• Flexible PTO in US
• Parental Leave
• Benefits (medical, dental and vision)
• Flexible Spending Accounts
• 401k/Pensions
• Gym Access
• Flexible Working Hours- Familiarity with the unique power and thermal challenges of high-density AI clusters—including 48V power delivery and high di/dt transients
• PCIE Gen5/6 and 100g Ethernet Expertise
• 10+ years of experience in high-speed digital design or hardware validation within a data center, systems architecture, or server bring-up environment
• Deep knowledge of high-speed protocol physical layers (PCIe, IEEE 802.3) and low-speed control buses (I2C, SPI)
• Strong fundamentals in digital circuit design, debug, and computer architecture
• Programming fluency in Python or equivalent scripting languages (Perl, Shell)
• Hands-on mastery of high-bandwidth real-time oscilloscopes, VNAs, and logic analyzers
• Expert-level proficiency in SI/EM tools: Ansys HFSS/SIwave, Cadence Sigrity/Allegro, or Keysight ADS
• B.S. or M.S. in Electrical Engineering (M.S. preferred)
• Hands-on experience validating GPU/TPU modules or AI-specific interconnects such as NVLink or CXL
• M.S. or Ph.D. with emphasis in Electromagnetics, Computer Architecture, or Power Electronics
• Ability to build end-to-end automated test frameworks in Python or TCL, integrating lab equipment with Pandas/NumPy for rapid correlation
• Transaction- and link-layer expertise in PCIe Gen5/6 and DDR5—not just physical layer knowledge