Senior Integration & Yield Engineer

Who you are

• Master's degree or Ph.D. in Physics, Materials Science, or a related field
• 3+ years of hands-on experience in semiconductor or superconducting circuit nanofabrication or process integration
• Proven expertise in yield engineering, SPC, DOE, and statistical analysis tools
• Proficiency in Python scripting to adapt and extend tools connecting design and fabrication workflows
• Strong problem-solving mindset and command of root cause analysis methodologies (5 Whys, FMEA, Ishikawa)
• Excellent communication skills and the ability to work effectively in a cross-disciplinary environment
• Experience in the fabrication or characterization of superconducting circuits, or in cryogenic testing is a plus
• This list is a guide, and we'd love to receive your application even if you think you're only a partial match

What the job involves

• We are seeking a Senior Integration & Yield Engineer to join the Foundries & Process Integration team within the Quantum Hardware & Infrastructure department
• The role sits at the interface between qubit design and the chip manufacturing teams. Its purpose is twofold: ensure that device designs translate reliably into high-performing fabricated circuits, and provide the data foundation for process improvement decisions
• You will own yield monitoring across our fabrication flows, lead the analysis of fabrication and test data, and maintain the interfaces between design and manufacturing — supporting the scale-up from tens of qubits to a few hundred, and enabling our path toward fault-tolerant quantum computing
• Yield engineering & data analysis
• Own yield monitoring across fabrication flows: define metrics, build automated dashboards (wafer reports), and provide real-time visibility of fab performance and yield
• Lead root cause analysis of systematic and random yield detractors, in collaboration with the chip manufacturing teams
• Perform advanced statistical analysis (using Python/JMP) to ensure process stability and control variability
• Develop strategies to reduce inductance/frequency non-uniformity within and across wafers, improving the consistency of qubit performance (frequency targeting, coherence times)
• Process Integration
• Define and maintain robust integration flows of POR (process of reference), ensuring design-to-fab alignment
• Establish Design for Manufacturability (DFM) guidelines
• Document and maintain reference fabrication flows, yield dashboards, and process KPIs to support process reviews
• Design-to-fabrication interface
• Own the look-up tables (LUT) linking design parameters to Josephson junction fabrication, and maintain their accuracy as fabrication processes evolve
• Test and implement Design Rule Manual (DRM) extensions in collaboration with the design and fabrication teams, and establish Design for Manufacturability (DFM) guidelines
• Translate device designs into fabrication-ready wafer layouts (wafer layout generation), and develop Python-based tools to automate the design-to-wafer pipeline and reduce manual handoff errors
• Failure analysis coordination & continuous improvement
• Coordinate the investigation of device failures at room and cryogenic temperatures using electrical test data, inline metrology, and advanced microscopy (SEM, AFM)
• Lead corrective and preventive actions using structured problem-solving methodologies (5 Whys, Ishikawa)

The application process

• Screening Call with Alexandra, Talent Acquisition Specialist (30 min)
• Hiring Manager Interview with Alireza (45 min)
• Technical Interview/Presentation with the Team (120 min)
• Leadership Team Interview (45 min)
• Fit Interview (45 min)
• Reference check