Senior Layout Engineer

Senior Layout Engineer - Istanbul (On-site) - Semiconductor

Our client is a growing semiconductor company driving innovation in high-performance integrated circuits. They are seeking an experienced Senior Layout Engineer to take ownership of physical layout design and tape-out execution for advanced analog and mixed-signal IPs. Working closely with IC design engineers, you will ensure that physical implementations strictly align with circuit requirements to maximize silicon performance and yield.

What You’ll Do:

• Full-Cycle IP Layout Execution: Lead and execute physical layout design for a wide range of analog modules (including Bandgap, ADC/DAC, LNA, PLL, DC-DC converters, and LDOs) from initial floorplan to final tape-out.
• High-Speed & RF Optimization: Design layouts for high-performance, high-speed signals, actively collaborating with circuit designers to meet tight constraints on parasitics, matching, and signal integrity.
• Floorplanning & Noise Suppression: Apply robust layout floorplanning techniques, optimizing for parasitic reduction, latch-up prevention, and noise isolation across sensitive analog blocks.
• Physical Verification: Perform complete layout verification using industry-standard tools (Virtuoso, Calibre, PVS) within a Linux environment, driving DRC, LVS, and antenna sign-off.
• Cross-Functional Collaboration: Serve as a key link between circuit design and foundry requirements, troubleshooting issues early in the design cycle to maintain project timelines.

Essential Requirements:

• Education: Bachelor’s degree or higher in Electrical/Electronic Engineering or a related technical discipline.
• Experience: 3+ years of hands-on experience in analog IC layout design, with a track record of successful full project tape-outs. Top-level layout ownership across multiple foundry process nodes is strongly preferred.
• Tool Proficiency: Solid operational command of Cadence Virtuoso, Siemens Calibre, and/or Cadence PVS in a Linux desktop environment.
• Deep Domain Knowledge: Strong understanding of semiconductor device physics, analog matching rules, latch-up mechanisms, ESD, I/O considerations, and packaging constraints.
• Languages & Soft Skills: Good written English (fluent spoken English is highly desirable), paired with strong analytical troubleshooting skills and a proactive project ownership mindset.

Desirable Extras:

• Experience with ultra-high-speed chip layouts, RF processes, or BCD (Bipolar-CMOS-DMOS) technology nodes.
• Familiarity with advanced-node parasitic extraction (PEX) and post-layout simulation loops.