Senior Layout Engineer

Senior Custom Memory Layout Engineer – Periphery & Macros

Contract: 12 Months

Location: Santa Clara, CA

Work Setting: Onsite initially; hybrid may be possible after ramp-up

Role Overview

Seeking a Senior Custom Memory Layout Engineer to develop and integrate memory periphery, sense circuitry, control structures, test structures, and memory macros in advanced CMOS technologies. The role requires deep hands-on custom layout experience and close collaboration with circuit and physical-design teams.

Responsibilities

• Create custom layouts for memory periphery, test structures, and memory macros.
• Develop block floorplans, routing strategies, power grids, and macro interfaces.
• Translate schematics into high-quality physical layouts while maintaining matching, symmetry, shielding, and parasitic requirements.
• Perform and debug DRC, LVS, ERC, antenna, and physical verification.
• Support EM/IR, DFM, density/fill, dummy insertion, and tapeout requirements.
• Resolve integration, pin-access, boundary, routing, and top-level physical-design issues.
• Work with circuit design, CAD, PnR, integration, and foundry teams.
• Review designs and mentor less-experienced layout engineers.

Required Qualifications

• 10+ years of hands-on custom IC layout experience.
• 5+ years working with SRAM, memory IP, or custom digital memory layout.
• Direct experience creating custom layouts rather than primarily managing layout teams.
• Experience with TSMC 3nm or more advanced process technology .
• Strong Cadence Virtuoso experience.
• Strong Calibre, ICV, or equivalent physical-verification experience.
• Experience with floorplanning, routing, macro assembly, pin planning, and block/top-level integration.
• Knowledge of advanced-node effects including LOD, density/fill, EM/IR, DFM, matching, and parasitic control.
• BSEE or equivalent experience.

Preferred

• Experience with TSMC, Samsung, Micron, or other advanced semiconductor organizations.
• Beyond-3nm experience.
• Experience with memory compilers or reusable memory IP.
• Exposure to AI-assisted custom-layout methodologies.