Senior Layout Engineer | Analog / Mixed-Signal IC Layout / Semiconductor Design

Senior Layout Engineer | Analog / Mixed-Signal IC Layout / Semiconductor Design

We are currently partnered with a growing semiconductor company developing high-performance analog and mixed-signal integrated circuits for advanced applications. As part of their continued product development, they are looking to hire a Senior Layout Engineer to take ownership of physical layout implementation and tape-out activities for complex analog and mixed-signal IP.

Key responsibilities

• Lead and execute full-cycle physical layout for complex analog and mixed-signal IP from initial floorplanning through final tape-out.
• Develop layouts for analog blocks including Bandgaps, ADCs, DACs, LNAs, PLLs, DC-DC converters, LDOs, and related circuit blocks.
• Work closely with analog and RF circuit designers to translate circuit requirements into robust physical implementations.
• Optimise high-speed and sensitive signal paths for parasitics, matching, signal integrity, noise, and overall circuit performance.
• Develop floorplans that minimise parasitic effects, optimise area, improve routability, and maintain critical device matching requirements.
• Implement effective noise isolation, shielding, guard rings, latch-up prevention, and other layout techniques for sensitive analog circuitry.
• Perform comprehensive physical verification using industry-standard tools including Cadence Virtuoso, Siemens Calibre, and Cadence PVS.

Key requirements

• Bachelor's degree or higher in Electrical Engineering, Electronic Engineering, Microelectronics, or a related technical discipline.
• 3+ years of hands-on experience in analog or mixed-signal IC layout design.
• Proven track record of contributing to or owning successful semiconductor tape-outs.
• Strong experience with full-cycle analog layout from floorplanning through physical verification and tape-out.
• Practical proficiency with Cadence Virtuoso, Siemens Calibre, and/or Cadence PVS.
• Comfortable working within Linux-based IC design environments.
• Strong understanding of semiconductor device physics and analog layout principles.
• Experience with high-speed or ultra-high-speed analog and mixed-signal layouts.
• Background in RF IC layout or high-frequency semiconductor design.
• Experience working with RF, BCD, or other specialised semiconductor process technologies.

Keywords

Senior Layout Engineer / IC Layout Engineer / Analog Layout Engineer / Mixed-Signal Layout Engineer / Physical Layout / Analog IC Layout / Mixed-Signal IC / Semiconductor / ASIC / Integrated Circuits / IC Design / Tape-Out / Floorplanning / Physical Verification / DRC / LVS / Antenna / PEX / Parasitic Extraction / Post-Layout Simulation / Cadence Virtuoso / Siemens Calibre / Cadence PVS / Linux / Analog Layout / RF Layout / High-Speed Layout / High-Frequency Layout / Bandgap / ADC / DAC / LNA / PLL / LDO / DC-DC Converter / BCD / CMOS / Semiconductor Device Physics / Matching / Parasitics / Signal Integrity / Noise Isolation / Latch-Up / ESD / Foundry / Process Nodes

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