Senior Layout Engineer(J10003)

该职位来源于猎聘 工作职责: Design the analog layout in power management products. Design includes low & high voltage CMOS layout design and DRC, LVS verification. Finish analog IC top layout and DRC, LVS verification independently. 任职资格: Bachelor or Master Degree with knowledge in analog IC layout design. At least 5 years working experience in CMOS process

Good knowledge in design of IC analog top and block layout.

Able to work in a team with good written and communication skills. Able to finish project layout independently. Preferably with high voltage BCD process experience.