Senior PCB Layout Engineer

Job Summary

We are seeking an independent Senior PCB Layout Architect to own the end-to-end design of complex, multi-layer printed circuit boards. In this role, you will implement cutting-edge high-speed interfaces, RF circuitry, and High-Density Interconnect (HDI) structures. You will translate schematic concepts into high-performance, manufacturing-ready physical hardware capable of supporting PCIe Gen 4/5, LPDDR4/4X/5, and USB 3.2+ standards.

Key Responsibilities

• End-to-End Layout: Own the complete layout lifecycle independently, from floor planning and component placement to final manufacturing release.
• Advanced HDI Design: Design complex multi-layer HDI PCBs using microvias (stacked/staggered), blind/buried vias, via-in-pad, and fine-pitch BGA escape topologies.
• Next-Gen Interface Routing: Execute channel-optimized routing for LPDDR4/4X/5 memory, PCIe Gen 4/5 channels, USB 3.2/USB4, HDMI 2.1, and Gigabit Ethernet.
• Constraint & Rule Setup: Utilize advanced constraint editors to define and validate strict physical, electrical, and spacing design rules.
• Stack-up & Material Selection: Collaborate on optimal layer stack-ups and hybrid material selection (e.g., Rogers, Isola, Megtron paired with FR-4) tailored for signal loss and thermal requirements.
• DFx Compliance & Deliverables: Apply strict DFM/DFA/DFT rules to generate production packages, including Gerber, ODB++, BOM, and Pick-and-Place data.
• Vendor Coordination: Partner with fabrication and assembly vendors to handle technical queries (EQs), validate panelization, and optimize manufacturing yields.

Skills & Technical Competencies

• ECAD Environments: Mastery of Cadence Allegro PCB Designer, OrCAD PCB Designer, and Cadence Constraint Manager.
• Low-Power Memory Architecture: Expert knowledge of LPDDR layout constraints (point-to-point topologies, quiet power rails, and tight data byte/command lane skew matching).
• IPC Standards: Working knowledge of industry-standard design, fabrication, and assembly rules
• PCB Material Science: Understanding laminate properties ((D_{k})/(D_{f}), glass transitions, weave styles for fiber-weave skew mitigation, and copper types for skin-effect loss).
• Signal & Power Integrity (SI/PI): Strong grounding in transmission line theory, controlled impedance, crosstalk mitigation (3W rule), backdrilling, and low-impedance PDN design.
• EMI/EMC Engineering: Practical skill in layout techniques to minimize radiated emissions and ensure compliance (shielding, isolation moats, stitching via fences).

Qualifications & Experience

• Experience: 5 to 8 years of proven experience in high-speed, multi-layer, and HDI PCB layout design.
• Education: B.E. / B.Tech / B.Sc. in Electronics & Communication Engineering, Electrical Engineering, or a Diploma in Electronics with equivalent experience.
• Certifications (Preferred): Active IPC CID or CID+ credential is a strong plus