Senior PDK Engineer

We are looking for design enablement experts who can demonstrate a strong background in semiconductor design enablement mainly for advance process and package (3DIC, CoWoS) PDK and RC extraction development.

Main Requirements and Qualifications

• PDK Development: Proven experience in developing, maintaining, and validating Process Design Kits (PDKs) for advanced silicon or packaging processes using Cadence or Synopsys platforms.
• Physical Verification: Strong proficiency in coding and debugging physical verification rule decks, including DRC (Design Rule Check), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check), and LPE (Layout Parasitic Extraction).
• RC Extraction Methodology: Demonstrated experience in leading the development, enhancement, and validation of RC extraction flows for complex physical designs.
• Advanced Package Enablement: Knowledge of and experience with heterogeneous integration and advanced packaging technologies, such as 3DIC,CoWoS, or CPO.
• Place & Route Technology: Experience with the development and maintenance of Place and Route (P&R) TechFiles for digital implementation flows.
• Collaborative Skills: Excellent communication and collaboration skills, with a track record of working effectively with foundries, EDA vendors, and internal design teams.
• Preferred Qualifications (Plus):
• Familiar with 3DIC, CoWoS PDK/Technology file development
• Familiar with EDA tools, Cadence SKILL, Tcl, Python or any script coding
• Familiar with STA timing analysis
• Familiarity with Figure of Merit (FOM) analysis and its application to Design-Technology Co-Optimization (DTCO).