Senior Physical Design Engineer

Who you are

• BS degree in electrical engineering, computer engineering, or a related field with 5+ years of experience in block or full-chip physical design, or
• MS degree in the above fields with 5+ years of related experience
• Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough
• Experience in developing and implementing power-grid and clock network at block level
• Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes
• Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at block level
• Experience in custom place and route
• Exposure to 2.5D/3D packaging is preferred
• High performance and large chip design experience is preferred
• Exposure to DFT is preferred
• Proficiency in writing Linux shell scripts in Perl, TCL, and Python
• Real chip tapeout experience in 7nm and/or below with a successful signoff track record
• Self-motivated with strong problem-solving and debugging skills
• Ability to work effectively in a dynamic group environment

What the job involves

• As a block-level and top-level SOC Physical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII
• Implement physical design at the large SoC block level from RTL to GDSII, creating a design database ready for manufacturing
• Build floorplan, including macro placement and optimization, block pins placement and alignment, power grid, and RDL design, etc
• Perform block-level place and route, including custom place & route, ensuring the design meets timing, area, power constraints, and all sign-off criteria
• Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification
• Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements
• Run Physical Design verification flow at block level, fixing LVS/DRC/ERC/ANT violations
• Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts

Benefits

• The chance to earn an annual bonus based on performance
• Recognition for your contributions, and potential participation in long-term incentives like annual equity awards
• Subsidized health insurance, retirement programs and paid time off, including an industry-leading maternity and paternity leave package
• A hybrid, flexible work model that ensures connectivity, a commitment to our culture and continued impact for team members
• Opportunities for personal and professional development to help you reach your career goals