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Senior Physical Design Engineer

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Remote

Senior Physical Design Engineer

European Tech Recruit

Senior Physical Design Engineer

Skills

NodeR

2 months ago

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Important information


Contract type:

Permanent

Location:

Canada

Work mode:

Remote

Published on:

3 September 2026

What they need


We are looking for a Senior Physical Design Engineer to join a growing engineering team in Ottawa. In this role you would take ownership of backend implementation from netlist through to GDSII across challenging ASIC blocks and sub-systems.

You will work with advanced physical design flows and single-digit FinFET technology nodes, collaborating with an experienced engineering team to deliver complex designs through to successful closure.

This is a fully remote senior-level position, open to candidates based anywhere.

Key Responsibilities

  • Own place & route implementation and analyze physical design results.
  • Develop effective floorplans to support physically-aware synthesis.
  • Drive designs through timing closure and physical verification.
  • Debug issues across EDA tools, timing constraints, DFT, and RTL/design implementation.
  • Work closely with front-end design teams to improve RTL quality and implementation efficiency.
  • Implement timing ECOs and optimize designs for performance.
  • Run PrimeTime and analyze timing reports.
  • Develop strategies to optimize power, performance, and area (PPA).
  • Perform IR-drop analysis and implement optimization strategies.
  • Collaborate with analog, front-end, and other physical design teams to align implementation objectives.

Key Qualifications

  • 8+ years of experience in ASIC digital physical design / place & route.
  • Strong hands-on experience with leading Synopsys and Cadence EDA tools and flows.
  • Experience working with advanced FinFET technology nodes, including DRC rules and node-specific P&R requirements.
  • Strong practical experience in floorplanning and physical implementation.
  • Solid understanding of Clock Tree Synthesis (CTS) and clock design for timing closure.
  • Experience with IR-drop analysis and optimization.
  • Strong background in timing closure and ECO implementation; PT-ECO or Tweaker experience is a plus.
  • Strong scripting and automation skills.
  • Experience with several of the following: synthesis, StarRC, PrimeTime DMSA, RedHawk, Calibre, LEC, or Formality.
  • A self-motivated, proactive approach with the ability to work effectively both independently and as part of a collaborative engineering team.

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