Senior Physical Design Engineer

Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design.

As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents.

We are looking for an experienced Physical Design / Static Time Analysis (PD/STA) Engineer to work onsite in our St. Paul, MN office to support ASICs, IPs and Chiplet designs. This role is targeted at mid-level candidates who can run RTL2GDS PD implementation and sign-off for tape out.

Key Responsibilities

• Perform synthesis, block and chip level implementation with industry standard PnR, STA and EMIR flows and tools.
• Implement entire ASIC place & route methodology, including floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification.
• Optimize designs through analysis, debug and fixing of Power and SI, LVS, DRC, ERC and antenna issues.
• Demonstrate proficiency with at least one of the industry EDA tool suites – Cadence, Synopsys, Siemens, Ansys, etc.
• Collaborate with cross functional teams, problem solving, teamwork and adaptability to new or changing tools, flows and methodologies.

Qualifications

• Bachelors or Masters in Electrical or Computer Engineering; related degrees may be considered if candidate has PD/STA experience
• 7+ years experience as a Physical Design and/or STA engineer
• Strong understanding of SOC/ASIC design flows, tools, and methodologies.
• Experience with advanced technology nodes and understanding of deep sub-micron design problems/solutions.
• Proficiency in STA techniques for timing, noise and timing-ECOs closure.
• Knowledge of low power design flows such as power gating, multi-Vt, Voltage scaling techniques
• Strong programming skills in Tcl/Perl/Shell/Python
• US Citizenship

What We Offer

• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off
• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO
• Incentives: Eligibility for short-term and long-term incentive programs

Join ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world.