Senior Physical Design Engineer

• Responsible for implementing RTL-to-GDSII process flow for block-level or full-chip SoCs.
• Communicate closely with the front-end design team to ensure the physical feasibility of the design modules.
• Analyze the backend design process for timing and congestion and optimize PPA from an implementation perspective.
• Responsible for various sign-off tasks, such as STA/IR/EM/PV, etc.
• Manage and track the backend status of team members, identify risks, provide effective solutions, and drive risk elimination.

Job Requirement

• Bachelor or MS Degree in EE or related disciplines
• Experience of working on top level design with chip level floor plan
• Familiar with Cadence EDI, Synopsys ICC design flow and Mentor Calibr
• Experience in advanced process nodes below 7nm is preferred
• Have complete experience in chip tapeout and be able to solve complex problems
• Familiar with TCL/ Perl scripting and design automation

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