Senior Physical Design Engineer

Are you passionate about building next-generation semiconductor products and driving designs from RTL to Tape-out? Join our team and work on cutting-edge ASIC/SoC development programs.

What You'll Do

• Execute full-chip Physical Design, Synthesis, Physical Verification, and Timing Closure
• Setup and synthesize RTL designs
• Drive timing closure using advanced optimization techniques, with strong expertise in Top-Level STA
• Perform EM/IR Analysis and power integrity validation
• Execute Place & Route activities for complex SoCs
• Lead Clock Tree Synthesis (CTS) , custom clock tree implementation, skew balancing, and insertion delay optimization
• Handle Floorplanning and Layout , including top-level floorplan architecture and implementation
• Develop and improve physical design flows, methodologies, and automation
• Collaborate closely with RTL, Design, Verification, and Architecture teams

What We're Looking For

• Strong expertise in RTL-to-Tapeout Physical Design Flow
• Hands-on experience with industry-standard EDA tools (Innovus)

Solid experience in:

• Synthesis
• Floorplanning
• Place & Route
• CTS
• STA & Timing Closure
• Physical Verification
• EM/IR Analysis
• Strong scripting skills in TCL and/or Perl

If interested, please share your resume on [email protected].