Senior Physical Design Engineer/Lead

Roles and Responsibilities :

• Design and develop physical designs for complex digital circuits using STA (Static Timing Analysis) techniques.
• Collaborate with cross-functional teams to ensure successful project delivery, meeting customer requirements and timelines.
• Perform thorough analysis of circuit behavior, identifying areas for optimization and implementing improvements through PNR (Performance, Power, Area) tradeoffs.
• Develop expertise in floor planning tools such as Synopsys VCS or Cadence NC-VLSI to create efficient chip layouts.

Job Requirements :

• 5-15 years of experience in Physical Design Engineering with a focus on STA/PDR (Physical Design Review).
• Strong understanding of static timing analysis (STA) principles and its application in semiconductor industry.
• Proficiency in one or more EDA vendors' software such as Synopsys VCS or Cadence NC-VLSI for floor planning and routing tasks.