Senior Principal Engineer

Key Responsibilities

• Lead the micro-architecture and RTL design of the PCIe subsystem from PHY/MAC through Transaction Layer and internal fabric interfaces.
• Oversee PCIe IP integration, managing lane/bifurcation logic, TLP pipelines, flow control, arbitration, and error handling processes.
• Define and implement PCIe-to-internal-fabric and TLP-to-flit interfaces, ensuring interfaces meet performance and timing requirements.
• Drive critical design processes such as timing closure, clock domain crossing (CDC), reset domain crossing (RDC), power management, and design verification (DV).
• Lead architectural reviews, ensuring that design methodologies align with industry standards and company objectives.
• Mentor and guide RTL engineers, fostering a culture of technical excellence and continuous learning within the team.
• Collaborate with design verification, physical design, firmware, and customer teams to ensure seamless integration and interoperability of PCIe subsystems.
• Lead the PCIe micro-architecture specification process, ensuring comprehensive documentation and adherence to best practices.

Overview

• The Principal Engineer PCIe Lead will spearhead the design and integration of PCIe subsystems within next-generation chiplet-based System-on-Chips (SoCs) tailored for high-performance computing (HPC) and artificial intelligence (AI) applications.
• This role is pivotal in leading the PCIe architecture and micro-architecture development, ensuring alignment with performance and interoperability standards.
• The incumbent will oversee the RTL design processes, driving innovations in PCIe controller and PHY integration into production SoCs.
• Working closely with diverse teams, this position requires a collaborative approach to problem-solving and design optimization.
• Situated in Bangalore, this role offers a unique opportunity to influence cutting-edge semiconductor technologies.
• As a senior leader, the Principal Engineer will provide technical guidance and mentorship to RTL engineers, fostering a culture of excellence and innovation within the team.
• This strategic role demands an in-depth understanding of PCIe protocols and the ability to translate complex architectural requirements into robust design solutions.
• The successful candidate will ensure that all subsystem designs meet the highest standards of performance and reliability.
• Situated in the fast-paced semiconductor sector, this position offers the opportunity to work on transformative technologies that are at the forefront of the industry.

Requirements

• Minimum of 10 years experience in digital IC/RTL design, with at least 4 years focused on PCIe subsystem design and integration.
• Deep expertise in PCIe architecture and protocols, including Transaction Layer Packets (TLPs), flow control, and error handling.
• Proven experience in integrating PCIe controller/PHY hard IP into production SoCs, including wrapper RTL and reset/clock integration.
• Strong proficiency in SystemVerilog for RTL and micro-architecture design.
• Experience with multi-clock designs, clock domain crossing (CDC), asynchronous FIFOs, and managing high-bandwidth, latency-sensitive datapaths.
• Familiarity with PCIe compliance and certification processes, as well as silicon bring-up procedures.
• Knowledge of Compute Express Link (CXL) is highly desirable, along with experience in SR-IOV and multi-function device architectures.