Senior R&D Engineer / Specialist - Ti/Cu Sputtering

About the role

This role involves developing and optimizing seed metallization sputtering processes, establishing film and interface characterization methods, investigating defects, and integrating sputtering with downstream processes to ensure continuous and manufacturable metallization flow. You will provide qualification guidelines for PVD equipment, drive particle and contamination control, and prepare documentation to support pilot and high-volume manufacturing ramp.

Key responsibilities

• Develop and optimize seed metallization (such as Ti/Cu) sputtering recipes to meet film thickness, uniformity, sheet resistance, adhesion, stress and defect targets by controlling pre-clean, power, pressure, gas flow, deposition time and substrate handling through DOE
• Establish film and interface characterization methods to verify seed/barrier integrity by correlating process conditions with thickness mapping, sheet resistance, adhesion, morphology, contamination and reliability data
• Investigate defects such as poor adhesion, particles, arcing, non-uniformity, high resistance and coverage discontinuity to protect plating and electrical yield through structured chamber, target, surface and handling analysis
• Integrate sputtering with PiD descum, Cu plating and Ti/Cu etching to ensure a continuous and manufacturable metallization flow by defining surface condition, seed continuity and downstream compatibility requirements
• Provide qualification guideline for PVD equipment, targets, fixtures and preventive-maintenance concepts to establish safe and scalable capability by defining customer specification requirements/acceptance criteria, chamber matching and process-control plans
• Drive initial particle, contamination and chamber-health control to maintain stable film quality by monitoring critical consumables, target life, shields, vacuum performance and SPC indicators
• Prepare development and initial transfer documentation and act as supporting roles to TDI team in setting up pilot/HVM ramp to ensure repeatable execution by monitoring early lots and closing process deviations

About you

• Bachelor's or Master's degree in Materials Science, Physics, Vacuum/Surface Engineering, Electronics, Mechanical or a comparable technical discipline
• Typically 5+ years of relevant PVD/sputtering experience in semiconductor, advanced packaging, IC-substrate, display or related thin-film manufacturing; Ti/Cu seed/barrier experience is strongly preferred
• Strong PVD/vacuum knowledge including plasma, target behavior, film nucleation, stress, uniformity, adhesion, contamination and particle mechanisms
• Hands-on experience with sputtering tools, vacuum troubleshooting and film metrology such as thickness, sheet resistance, microscopy and adhesion testing
• Understanding of dielectric surface preparation, electroplating and seed-layer etch integration is strongly preferred
• Strong experimental planning, statistical analysis and structured problem-solving skills
• Structured DOE, SPC, MSA, FMEA and statistical data analysis; strong root-cause and problem-solving discipline
• Ability to translate product/customer requirements into measurable process specifications and acceptance criteria