Senior RTL Design Engineer

About The Company Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.

Anthriq Silicon is our ground-up effort to build a new compute category. Read More About Anthriq Silicon Program here: anthriq.com/silicon About The Role We are building a compute-heavy multi-core vector processor with a custom ISA. You will implement the execution units, register files, and data forwarding network that form the computational core of the processor.

Responsibilities

• Implement all execution units across the custom ISA (integer, floating-point, fixed-point,

complex arithmetic)

• Build multi-port register files (flip-flop-based, conflict-free, multi-read multi-write)
• Implement the bypass/forwarding network for hazard-free data delivery
• Integrate IEEE 754-compliant floating-point datapaths (half, single, double precision)
• Implement saturating arithmetic, configurable rounding modes, and extended-precision

accumulators

• Optimize critical arithmetic paths (carry-save adders, Wallace trees, Booth-encoded

multipliers)

• Work with the verification team to achieve per-opcode coverage across all supported data

types.

Requirements

• 5+ years RTL design in SystemVerilog
• Strong arithmetic unit design (multipliers, dividers, adders — not just instantiating IP)
• IEEE 754 floating-point implementation experience
• Fixed-point arithmetic, saturation modes, rounding modes
• Understanding of pipelining and multi-cycle datapath design
• Comfortable working from a detailed architecture spec

Nice to Have

• DSP datapath experience (MAC units, butterfly structures, CORDIC)
• Vector/SIMD lane design
• Experience with extended-precision or redundant arithmetic
• SoftFloat or similar reference model experience for FP verification

Skills: api,technology,asic design,ip,arithmetic,vector,systemverilog,rtl coding,data,silicon,forwarding,isa,design,signal,ieee,rtl design