Senior Staff Engineer – Memory Circuit Design

Senior Staff Engineer – Memory Circuit Design

Location: Bengaluru

Experience: 12–16 Years

Role Overview

We are seeking a technically strong Senior Staff Engineer with deep expertise in Memory Circuit Design, custom transistor-level design, and memory IP development. The role involves architecture, circuit implementation, optimization, and silicon validation of high-performance, low-power memory circuits.

Key Responsibilities

• Design and develop memory circuits and custom memory IP at the transistor level.
• Lead circuit design for SRAM and other memory architectures, including bitcells, sense amplifiers, write drivers, decoders, and peripheral circuits.
• Drive memory circuit architecture, schematic design, simulation, and design optimization for PPA.
• Perform transistor-level simulations, timing analysis, power characterization, and corner analysis across PVT conditions.
• Optimize memory circuits for performance, power, area, stability, and yield.
• Conduct SRAM bitcell stability analysis, including SNM, read/write margin, and assist techniques.
• Collaborate with layout, physical design, technology, and silicon validation teams to ensure robust implementation.
• Support post-silicon characterization, silicon debug, and correlation of simulation results with silicon measurements.
• Drive design reviews, resolve complex circuit-level issues, and provide technical guidance to the team.

Required Technical Expertise

• 12–16 years of hands-on experience in Memory Circuit Design or Custom Analog/Mixed-Signal IC Design.
• Strong expertise in SRAM circuit design , including bitcells, sense amplifiers, write drivers, decoders, and peripheral circuits.
• Deep understanding of CMOS transistor-level design and circuit analysis.
• Proficiency in SPICE-based simulations using Cadence Spectre, HSPICE, or equivalent tools .
• Experience with PVT, Monte Carlo, mismatch, variation, and statistical analysis.
• Strong knowledge of SRAM stability, timing, power optimization, and memory design trade-offs.
• Experience with schematic design, circuit verification, and layout-parasitic-aware optimization.
• Strong understanding of semiconductor device characteristics, CMOS process technologies, and design reliability.

Preferred Skills

• Experience with advanced technology nodes and high-density SRAM design.
• Exposure to low-voltage memory operation, assist circuits, and yield optimization.
• Experience in silicon bring-up, characterization, and silicon-to-simulation correlation.
• Strong technical ownership of complex memory circuit design challenges.

Education

B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics, or a related discipline.