Senior / Staff Synthesis Methodology Engineer

Position Overview:

We are looking for an experienced Synthesis Methodology Engineer to own and drive RTL synthesis methodologies across our AI SoC development projects. You will be responsible for developing, maintaining, and optimizing synthesis flows, evaluating new EDA tools, and enabling efficient implementation across multiple technology nodes.

You will collaborate closely with Design, Backend, CAD, and EDA vendors to improve design productivity and quality.

Responsibilities:

• Synthesis Flow Ownership: Develop, maintain, and optimize RTL synthesis flows using Synopsys Design Compiler to support ASIC/AI SoC development.
• Synthesis Methodology: Design and improve synthesis methodologies, automation, and reusable workflows across multiple projects and technology nodes.
• RTL Synthesis: Perform RTL synthesis for AI/NPU-related blocks while ensuring quality, performance, and design convergence.
• Sign-off Verification: Develop and maintain sign-off methodologies using PrimeTime, Formality, VC SpyGlass, and VCLP to ensure design integrity.
• Technology Migration: Support technology node migration, library updates, and flow enhancements to meet evolving project requirements.
• EDA Tool Evaluation : Evaluate, validate, and deploy new EDA tools and methodologies such as Synopsys Fusion Compiler and Cadence Genus.
• Automation & Scripting: Develop scripts and automation to improve synthesis productivity, flow robustness, and engineering efficiency.
• Cross-functional Collaboration: Work closely with RTL designers, Backend, CAD, and EDA vendors to resolve synthesis, timing, and methodology issues.

Qualification/ Requirements:

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Minimum 5 years of experience in ASIC/SoC RTL synthesis or synthesis methodology development.
• Strong hands-on experience with Synopsys Design Compiler .
• Familiarity with sign-off tools such as PrimeTime, Formality, VC SpyGlass, and VCLP .
• Experience with RTL synthesis, timing optimization, synthesis constraints, and ASIC implementation flow.
• Proficiency in Tcl, Shell, or Python scripting for automation and flow development.
• Experience evaluating or deploying EDA tools such as Fusion Compiler or Cadence Genus is highly preferred.
• Strong analytical, debugging, and problem-solving skills.
• Good communication skills with the ability to collaborate effectively across cross-functional engineering teams.