Senior substrate layout engineer

• Advanced Package BGA substrate layout and PV (DRC; LVL; LVS) check 2. 2.5D IC (CoWoS_S; CoWoS_L; CoWoS_R; EMIB) RDL & Sbustrate routing and PV check. 3. Co-work with package Design engineer to achive PKG design requirement and goal. 4. New PKG layout methodology Study and development. 5. New layout & PV EDA tool evaluation

Main Requirements and Qualifications

• 1. Bachelor's degree or above with major in EE, ME, or related engineering fields.
• 2. Familiar with Cadence APD/SiP or Siemens XPD PKG layout tools and operating those tools smoothly.
• 3. Familiar with the design flow of package design and RDL/SBT layout
• 4. Familiar and well known with the structures of FCCSP/FCBGA/HBPOP/PKG Module.
• 5. Experienced on CoWoS structure and Interposer/RDL/SBT design is plus.
• 6. Experienced on Cadence APD skill language development is a plus.
• 7. Familiar with PKG PV (DRC, LVS) check flow and tools (Calibre, 3DStack) is a plus