Senior Validation Engineer

Role Overview:

Seeking a senior-level engineer with strong hands-on experience in ATE production test development for SoC devices with co-packaged optics (CPO) and high-speed SerDes interfaces.

Key Responsibilities:

• Develop and maintain wafer sort and final test programs using Advantest V93K or Teradyne UltraFLEX.
• Develop SerDes production tests covering PRBS, BER, loopback, CDR, equalization, jitter, and margining.
• Integrate DFT/BIST, scan/ATPG, MBIST/LBIST, and JTAG patterns into ATE test flows.
• Implement production checks for UCIe and PCIe Gen5/Gen6 interfaces.
• Optimize multisite testing, yield, test coverage, and test time.
• Correlate characterization and bench results with ATE production data.
• Develop Python automation tools for STDF parsing, data analytics, SPC, and anomaly detection.
• Collaborate with design, firmware, DFT, product engineering, and OSAT teams.

Required Skills:

• Strong hands-on ATE development experience.
• SerDes PHY and high-speed interface testing.
• DFT/BIST, scan/ATPG, JTAG, and pattern conversion.
• Python scripting, STDF analytics, and yield optimization.
• Working knowledge of UCIe and PCIe protocols.