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Senior Verification Engineer - ASIC / UVM

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Senior Verification Engineer - ASIC / UVM

European Tech Recruit

Senior Verification Engineer - ASIC / UVM

2 months ago

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Important information


Contract type:

Permanent

Location:

Athens, Greece

Work mode:

Onsite

Published on:

26 August 2026

What they need


Senior Verification Engineer - ASIC / UVM

We are partnered with a global leader in embedded processing and microcontroller solutions for automotive, industrial, and IoT markets. The team is looking to hire a Senior Verification Engineer to lead end-to-end verification of complex IC blocks and systems, owning strategy, environment development, and closure.

This is a permanent, hybrid opportunity based in Athens, Greece.

Key responsibilities for this Senior Verification Engineer position:

  • Architect and execute comprehensive verification strategies, test plans, and UVM-based environments from scratch.
  • Drive functional and code coverage to closure using constrained-random testing, SVA, and formal methods.
  • Review design specifications early in the cycle to improve quality and verification fitness.
  • Partner with global architecture, design, and software teams to optimise hardware/software partitioning and system-level verification.
  • Mentor junior engineers and champion design and verification reviews.
  • Evaluate third-party VIP and tools to drive make/buy decisions and maximise engineering efficiency.

Key requirements:

  • Extensive experience in ASIC/IC digital verification with strong mastery of SystemVerilog and UVM.
  • Proven ability to build UVM testbenches from scratch, translating specifications into full verification environments.
  • Proficiency with industry-standard simulators and management tools — Cadence Xcelium, eManager/vManager, or equivalent.
  • Solid grounding in functional verification, assertion-based verification (ABV), formal verification, and regression frameworks.

Keywords: Senior Verification Engineer / Digital Verification / UVM / SystemVerilog / ASIC / Functional Verification / Assertion-Based Verification / Formal Verification / Cadence Xcelium / SVA / Constrained Random / Regression / VHDL / Verilog / Athens / Greece / Hybrid / Permanent

If you are interested in this Senior Verification Engineer position, please send a copy of your CV to [email protected]

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