Senior/Lead STA Engineer

Role & responsibilities :

We are looking for a Senior / Lead STA Engineer with 5+ years of experience in Static Timing Analysis and signoff for advanced ASIC/SoC designs. The candidate will be responsible for timing analysis, constraint development, timing closure, and signoff across multiple PVT corners, working closely with RTL, Synthesis, Physical Design, and Design teams.

Preferred candidate profile

• Own STA and timing signoff for block/top-level designs.
• Perform setup, hold, recovery, removal, and min/max timing analysis across multiple PVT corners and modes.
• Develop, review, and debug SDC constraints including clocks, generated clocks, I/O delays, false paths, multicycle paths, and clock groups.
• Analyze timing reports and identify critical paths and timing bottlenecks.
• Drive timing closure in collaboration with synthesis and physical design teams.
• Debug timing violations related to:
• Cell delays and transitions
• Fanout and capacitance
• Clock skew/latency
• Congestion and physical effects
• SI/crosstalk
• OCV/AOCV/POCV variations
• Perform MMMC analysis and signoff across required scenarios.
• Work with implementation teams on ECOs for setup/hold closure.
• Review timing constraints and ensure consistency between RTL, synthesis, and implementation.
• Analyze clock-domain crossings and clock architecture from a timing perspective.
• Support STA flow development, automation, and methodology improvements using Tcl/Python.
• Participate in timing signoff reviews and communicate status, risks, and closure plans to project leads.
• Mentor junior STA engineers and provide technical guidance.