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SiC Device Design Engineer

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Onsite

SiC Device Design Engineer

Larsen & Toubro

SiC Device Design Engineer

Skills

Node

15 days ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

10 October 2026

What they need


Role

  • Lead the design and optimization of next-generation SiC MOSFETs and GaN power devices for automotive and industrial applications.
  • Benchmarking of critical design parameters in and across the voltage nodes.
  • Research and evaluate novel architectures to improve performance and reliability.
  • Define device architectures to achieve electrical, thermal, reliability, and cost targets.
  • Support development and calibration of TCAD process and device simulation models using experimental characterization data.
  • Design reliable edge termination structures for high and ultra-high voltage applications.
  • Lead prototype evaluation, electrical characterization, and silicon debug activities in collaboration with Failure Analysis and Reliability teams.
  • Optimize device designs considering process variation, manufacturability, and long-term reliability.
  • Collaborate with Process Integration, Product Engineering, Reliability, and external foundry teams throughout product development.
  • Support in IP generations, technical report writing, and research publications.
  • Provide technical guidance to junior engineers and review technical deliverables.
  • Clear communication of complex technological ideas to cross functional and leadership teams.

Requirements

  • MS/PhD in Electrical Engineering, Microelectronics, Semiconductor Physics, or a related discipline.
  • 6–10 years of experience in power semiconductor device design.
  • Strong expertise in SiC MOSFETs, SiC diodes, GaN HEMTs, or advanced silicon power devices.
  • Advanced knowledge of semiconductor device physics and wide bandgap materials.
  • Expert-level experience with TCAD simulation and model calibration.
  • Experience in device layout development and mask design.
  • Strong understanding of silicon correlation and electrical characterization.
  • Knowledge of reliability mechanisms including TDDB, HTRB, HTGB, HTOL, UIS, avalanche, and short-circuit ruggedness.
  • Experience in JMP, Minitab, or other statistical tools.
  • Familiarity with JEDEC and AEC-Q101 qualification standards.
  • Experience collaborating with external foundries are desirable.

Patent contributions or published technical work are desirable

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