HCLTech
Signal Integrity Engineer
Skills
2 months ago
Share this opportunity
Share this opportunity to other talents of your network:
✓ Offer them a visibility boost with clients.
✓ Help your contacts find their next job.
Important information
Contract type:
Permanent
Work mode:
Onsite
Published on:
16 August 2026
What they need
Onsite Meta Xinyi office
Signal Integrity Engineer
[Signal Integrity / Power Integrity (SI/PI) Engineer]
Role Overview
We're seeking an experienced SI/PI Engineer to join our Advanced Silicon Packaging team. In this role, you will be responsible for signal integrity and power integrity analysis, modeling , and design optimization of next-generation multi-die packaging architectures including 2.5D/3D integration, silicon interposers, and high-bandwidth memory (HBM) interfaces.
Responsibilities
- Perform SI/PI analysis and design optimization for advanced silicon packages ( CoWoS, EMIB, chiplet-based architectures, fan-out wafer-level packaging )
- Develop and validate high-speed channel models for package interconnects including bumps, micro bumps, TSVs, RDL layers, and silicon/organic interposers
- Conduct full-wave electromagnetic (EM) simulations of package structures to characterize S-parameters, crosstalk, impedance, and insertion/return loss
- Design and optimize Power Distribution Networks (PDN) — including decoupling strategy, IR drop analysis, and AC impedance profiling from die to board
- Perform time-domain simulations (eye diagram, BER analysis) for high-speed serial and parallel interfaces (PCIe Gen5/6, UCIe, HBM3/3E, DDR5, SerDes >112 Gbps)
- Collaborate with IC design, package substrate design, PCB layout, and thermal/mechanical teams to co-optimize package electrical performance
- Develop and correlate simulation models with lab measurements (VNA, TDR, oscilloscope, power noise measurements)
- Define SI/PI design guidelines and constraints for package substrate stack-up, routing rules, and bump/via assignments
- Support design-for-manufacturability (DFM) reviews with OSAT partners and substrate vendors
- Investigate and resolve SI/PI-related failures during silicon bring-up and validation phases
- Co-work with Meta U.S. Development team in US, India or Taiwan.
- Business Travel to Hsinchu occasionally.
Min. Qualifications
- 5+ yrs of exp. in SI/PI analysis for Semiconductor Packaging or High-speed PCB design
- Strong proficiency with industry-standard EM and Circuit Simulation tools :
○ EM Solvers: Ansys HFSS, Ansys SIwave, Cadence Clarity 3D, Keysight ADS Momentum
○ Circuit Simulation: Synopsys HSPICE, Cadence Spectre, Keysight ADS
○ PDN Analysis: Ansys RedHawk, Cadence Voltus, Sigrity PowerDC/PowerSI
- Deep understanding of Transmission line Theory , Maxwell's Equations , and S-parameter Analysis
- Exp. w/ High-speed Interface protocols (PCIe, UCIe, HBM, DDR, Ethernet SerDes)
- Proficiency in Package stack-up Design, Impedance control , and via Transition optimization
- Hands-on exp. w/ Measurement correlation (VNA, TDR/TDT, near-field scanning)
- Programming/scripting skills (Python, MATLAB, TCL) for Automation and Post-processing
Preferred Qualifications
- Exp. w/ 2.5D/3D Advanced Packaging technologies (CoWoS, EMIB, Foveros, Hybrid bonding)
- Familiarity w/ Chiplet-based Disaggregated architectures and Die-to-die interconnect standards (UCIe, BoW)
- Knowledge of Co-simulation Methodologies (Chip-package-board co-design)
- Exp. w/ Statistical analysis and Monte Carlo methods for Manufacturing variation impact
- Understanding of Thermal-aware electrical analysis (Electro-thermal co-simulation)
- Contributions to IEEE/DesignCon publications or industry standards committees (JEDEC, OIF, UCIe Consortium)
- Exp. working w/ OSATs (ASE, Amkor, TSMC InFO/CoWoS) and substrate vendors
Others
- Bilingual capability is required (Mandarin & English). Mandarin speaking/reading is essential skill in HCLTech Taiwan.
- Taiwan APRC is required w/ expat.
If interested, please apply w/ your updated English resume along with below details.
1. Total Years of Related Exp. -
2. Expected Annual Salary -
3. Notice period to join -
Why Us:
At HCLTech , we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.
Company page - https://www.hcltech.com/about-us
Other offers great for you!
These companies are also looking for great profiles
Mon Consultant Indépendant
Senior system engineer
TJM HT max 600 € (hors éventuels frais de mission, à discuter avec le client)
Freelance
Brussels, Belgium
Hybrid
Skills
20 hours ago
Quick apply
Equancy
Senior AI Engineer
Fourchette entre 54 et 63ke
Permanent contract
Paris, France
Hybrid
Skills
3 hours ago
Quick apply
LeHibou
SailPoint Engineer
750€ / jour
Freelance
Paris, France
Hybrid
Skills
3 hours ago
Quick apply
No company information available.