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SiP Process Engineer

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Onsite

SiP Process Engineer

UTAC

SiP Process Engineer

Skills

R

1 month ago

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Important information


Contract type:

Permanent

Work mode:

Onsite

Published on:

22 September 2026

What they need


Position Summary

We are looking for an experienced SiP (System-in-Package) Process Engineer to support the development, qualification, transfer, optimization, and high-volume manufacturing of SiP products.

The Process Engineer will be responsible for developing and optimizing SiP assembly processes, improving product quality and yield, troubleshooting manufacturing issues, and working closely with Design, Package Engineering, Equipment, Quality, Reliability, and Manufacturing teams.

The candidate should have strong knowledge of semiconductor packaging and assembly processes, hands-on problem-solving skills, and experience with process development and yield improvement.

Key Responsibilities

1. SiP Process Development

  • Develop and optimize SiP assembly processes from prototype through mass production.
  • Establish process flows, process parameters, specifications, and control plans.
  • Develop processes for multi-die and heterogeneous integration.
  • Support processes such as:
  • Die attach
  • Flip chip
  • Wire bonding
  • SMT/component placement
  • Underfill
  • Molding/encapsulation
  • Package singulation
  • Laser marking
  • Shielding
  • Rework and repair
  • Evaluate new materials, equipment, and process technologies for SiP applications.

2. New Product Introduction (NPI)

  • Support SiP product development from engineering samples to mass production.
  • Review package and product designs for manufacturability (DFM/DFA).
  • Develop process flow and process specifications for new products.
  • Lead engineering builds, DOE, process characterization, and process qualification.
  • Support product transfer from R&D or pilot line to mass production.

Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Electronics Engineering, Chemical Engineering, or a related field .
  • Typically 3–8+ years of semiconductor packaging, assembly, or SiP process engineering experience , depending on level.
  • Hands-on experience with semiconductor packaging/assembly processes.
  • Understanding of semiconductor manufacturing and process control.
  • Experience with DOE, SPC, FMEA, 8D, root-cause analysis, and statistical analysis .
  • Ability to analyze process data and identify correlations between process parameters and product performance.
  • Good technical problem-solving and communication skills.

Preferred Experience

Experience in one or more of the following areas is highly desirable:

  • System-in-Package (SiP)
  • Multi-chip modules (MCM)
  • Heterogeneous integration
  • Chiplet packaging
  • 2.5D/3D packaging
  • Flip-chip
  • Wire bonding
  • Die attach
  • SMT
  • Fan-out packaging
  • Package-on-Package (PoP)
  • Embedded die/package technologies
  • RF SiP
  • Automotive SiP
  • MEMS packaging
  • Advanced IC packaging

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