SoC實體設計工程師(新竹)

Location : 新竹科學園區

Work experience : 0 year

Education : 大學

工作項目：

1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs.

2. Responsible for Physical Design flow research, development and automation.

應徵條件：

1. 大學以上電機資訊相關科系畢

2. 熟悉 IC 後段設計流程, 具相關 APR 經驗者佳.

3. 對於開發及推廣 Physical Design Flow 有興趣者.

4. 熟悉相關 tools(Astro, Encounter, IC Compiler)者尤佳

5. 具程式設計(TCL,Perl,C/C++)能力者佳。