Soc Design Engineer

1. Strong experience in Design Integration for complex digital/SoC designs.
2. Good knowledge of Synthesis, Static Timing Analysis (STA), and Low Power Checks.
3. Good understanding of PLDRC and Clock Domain Crossing (CDC) analysis and debug.
4. Strong Python scripting skills for design automation and productivity improvement.

Good debugging, problem-solving, and design signoff experience

Preferred Qualifications:

• Master's degree in Computer Science, Electrical/Electronics Engineering, VLSI Engineering, or related field.
• 3+ years of Hardware Engineering or related work experience.
• Experience in ASIC/SoC design implementation and signoff methodologies.
• Familiarity with industry-standard EDA tools for synthesis, STA, CDC, low-power verification, and physical signoff.
• Experience with design automation using Python scripting.

Key Words

Design Integration, RTL Integration, SoC Integration, ASIC Design, Digital Design, Synthesis, Static Timing Analysis (STA), Timing Closure, Low Power Verification, UPF, CDC, Clock Domain Crossing, PLDRC, Signoff, Semiconductor Design, VLSI, Python Scripting, Automation, Hardware Engineering, Physical Design Checks.

Roles & Responsibilities

• Perform RTL and subsystem integration for complex RFIC/SoC digital designs.
• Execute synthesis, STA, timing closure, and low-power verification activities.
• Perform CDC analysis, debug violations, and ensure robust clock-domain interactions.
• Run PLDRC checks, analyze results, and drive closure of design rule violations.
• Develop Python scripts and automation frameworks to improve design flow efficiency.
• Collaborate with architecture, design, verification, and physical design teams to resolve integration and implementation issues.
• Support design quality, signoff activities, and deliverables across the project lifecycle.
• Participate in design reviews and contribute to methodology improvements and best practices.

Job Description

We are looking for a highly motivated Hardware Design Engineer to join our RFIC Digital Design team. The selected candidate will be responsible for design integration, synthesis, static timing analysis (STA), low-power verification, CDC validation, PLDRC, and automation activities for advanced semiconductor products.

The ideal candidate should possess strong experience in digital design implementation flows, timing analysis, and verification methodologies. The role requires close collaboration with cross-functional teams to ensure successful design integration and signoff. Strong Python scripting skills are essential to automate workflows and enhance engineering productivity.

The candidate should demonstrate excellent analytical, debugging, and communication skills, along with the ability to work effectively in a fast-paced semiconductor development environment