SoC Full Chip Verification Engineer

We are currently supporting a semiconductor client looking to hire an experienced SoC Full Chip Verification Engineer to work on the verification of advanced AI SoCs.

This position will focus on developing full-chip verification infrastructure and verifying complex end-to-end scenarios across CPUs, cache coherency, high-speed interfaces, memory and peripheral subsystems.

The role is suited to a hands-on verification engineer with strong experience in SystemVerilog/UVM, C/ELF-based verification, testbench development, VIP integration and verification sequences, with responsibility for driving functional and performance verification through to sign-off ahead of tapeout.

Responsibilities:

• Define and establish the SoC full-chip verification infrastructure and environment
• Develop reusable and generic testbenches for Chiplet-to-Chiplet and Package-to-Package verification
• Develop, integrate and work with models and VIPs for high-speed interfaces and peripherals
• Own and execute CI, sanity and full regression cycles
• Develop verification tests covering targeted end-to-end application scenarios
• Drive coverage closure across defined system-level use cases
• Perform functional verification and performance verification
• Verify complex interactions across CPUs, cache coherency, memory and high-speed interfaces
• Debug full-chip and system-level verification failures
• Support verification sign-off and ensure high-quality SoC delivery ahead of tapeout

Requirements:

• 6+ years’ experience in ASIC/SoC verification
• Proven experience achieving verification sign-off across multiple projects
• Strong expertise in SystemVerilog and UVM verification methodologies
• Experience with C/ELF-based verification
• Strong knowledge of CPUs and cache coherency
• Hands-on experience with protocols including PCIe, AXI, CHI, Ethernet and memory protocols
• Experience developing complex testbenches, verification sequences and integrating VIPs
• Strong understanding of functional coverage, regression and verification closure
• Experience with full-chip or system-level functional and performance verification
• University degree in Electrical Engineering, Computer Engineering or a related discipline
• Experience deploying AI agents within verification workflows would be highly advantageous