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SoC RTL Integration Engineer

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Onsite

SoC RTL Integration Engineer

Techlabs Semiconductor Pvt. Ltd.

SoC RTL Integration Engineer

Skills

PythonCompliance

2 days ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

24 October 2026

What they need


About the Company

Techlabs Semiconductor Private Limited is a wholly owned subsidiary company of Trident Techlabs Limited, a leading provider of semiconductor services offering comprehensive end-to-end solutions across design, verification, validation, testing, Systems Design, manufacturing and AI. We serve a diverse range of industries, including Consumer Electronics, Automotive, Semiconductor, Telecommunications, Defence, Armed forces and Industrial Automation.

About the Role

We are looking for an experienced SoC RTL Integration Engineer to drive IP and subsystem integration, develop top-level RTL wrappers, and ensure seamless connectivity across SoC components. The ideal candidate will have strong expertise in RTL integration, bus protocols, high-speed IPs, and static design checks, with the ability to collaborate effectively with cross-functional engineering teams.

Key Responsibilities

  • Develop and maintain top-level RTL wrappers, subsystem integration logic, and interconnect connectivity.
  • Integrate and validate high-speed IPs into subsystems and SoC designs, ensuring correct parameter configuration and protocol connectivity.
  • Work closely with RTL Design, Design Verification, DFT, Physical Design, Architecture, and Firmware/Software teams to deliver high-quality RTL.
  • Integrate standard interfaces and protocols, including AXI, AHB, APB, SPI, I²C, UART, and DMA.
  • Support integration of high-speed IPs such as DDR, Ethernet, and PCIe.
  • Perform lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis, and drive issue closure.
  • Perform static design checks and validate constraints from block to SoC level using tools such as SpyGlass and Fishtail.
  • Support synthesis activities, timing constraint development and validation, and Physical Design teams by delivering clean, synthesis-ready RTL.
  • Ensure compliance with low-power design methodologies and UPF requirements, where applicable.
  • Use scripting languages such as Perl, Tcl, and Python to automate integration tasks and improve design efficiency.
  • Coordinate with cross-functional stakeholders to resolve integration issues and meet project milestones.

Required Skills and Experience

  • 5–7 years of experience in RTL integration, SoC integration, or subsystem integration.
  • Hands-on experience with connectivity and integration tools.
  • Strong understanding of RTL design, IP integration, interconnects, and SoC architecture.
  • Experience integrating standard interfaces such as AXI, AHB, APB, SPI, I2C, UART, and DMA.
  • Practical experience with lint, CDC/RDC analysis, static checks, and constraint validation.
  • Familiarity with SpyGlass, Fishtail, or equivalent EDA tools.
  • Proficiency in at least one scripting language: Perl, Tcl, or Python.
  • Good communication and problem-solving skills, with the ability to collaborate across multiple engineering teams.

Good to Have

  • Experience integrating high-speed IPs such as DDR, Ethernet, or PCIe.
  • Exposure to CPU and XPU subsystem integration.
  • Knowledge of low-power design methodologies and UPF.
  • Experience supporting synthesis, timing closure, and Physical Design activities.

Educational Qualification

Bachelor's or Master's degree in Electronics, VLSI, Electrical Engineering, or a related discipline.

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