SOC數位IC驗證副理/經理(DV)

Location : 新竹科學園區

Work experience : 6 year

Education : 碩士

Key qualifications:

1. MS degree with EE or CS background

2. Familiar with SystemVerilog and Verilog

3. Exposure to OVM/UVM/VMM methodology

4. Exposure to constrained-random based verification environment

5. Exposure to create coverage model and drive coverage closure in including code/functional coverage.

6. Be able to develop a test bench from scratch

7. Hands on working experience on unit/block/full-chip level verification

8. Good communication skill

9. Leadership/management experience is a plus.

Job descriptions:

1. Plan the verification strategy for SOC projects

2. Hands-on verification task of some of the units

3. Work closely with the design teams.

4. Drive the verification team, problem-solving on day-to-day works

5. Provide the measurable metrics for project leads and upper management.

6. Bug/coverage trend identification. Foresee the possible issues and plan for them.

(MD17C0031)