Software Platform Architect – Hardware–Software Co-Design

Job Title: Software Platform Architect – Hardware–Software Co-Design

Experience: 15–20 Years

Location: Bangalore

Role Overview

Lead the end-to-end software platform architecture for next-generation AI accelerators, bridging silicon architecture, SDK development, compiler/runtime systems, ML frameworks, and production LLM inference. Drive hardware–software co-design, platform performance, and software ecosystem development.

Key Responsibilities

Own the software platform architecture, including runtime scheduler, memory manager, drivers, low-level APIs, compiler backend, and framework integration.

Define software architecture roadmaps, chip-generation compatibility, SDK governance, and platform performance benchmarks.

Collaborate with silicon teams to optimise memory usage, MIMD scheduling, HBM access, and overall accelerator performance.

Lead software bring-up planning and execution, from initial boot and PCIe validation to compute-unit testing, BF16 verification, and first LLM inference demonstration.

Drive integration with PyTorch, vLLM, HIP, Transformers, and DeepSpeed.

Establish porting strategies for CUDA, HIP, OpenCL, and MPI applications, including documentation and benchmarking.

Lead SDK CI/CD automation, regression testing, release management, coding standards, and technical documentation.

Mentor 5–10 engineers and collaborate with firmware, security, and external technology partners.

Required Qualifications

B.Tech/M.Tech or M.S./Ph.D. in Computer Science, Electrical Engineering, or a related field.

15–20 years of experience in software architecture for HPC, GPU, NPU, or many-core AI accelerator platforms.

Proven ownership of a production software stack from silicon bring-up to customer deployment, covering compiler backend, runtime, driver interfaces, and ML framework integration.

Strong C/C++ systems programming and Python scripting/tooling skills.

Hands-on experience with parallel programming technologies such as CUDA, HIP, OpenCL, MPI, and OpenMP.

Experience in hardware–software co-design, heterogeneous workload porting, and performance optimisation.

Preferred Qualifications

Experience building software ecosystems for non-NVIDIA/AMD accelerator platforms.

Familiarity with many-core architectures such as Tilera, Kalray, Graphcore IPU, custom HPC ASICs, or MIPS64 systems.

Experience with LLVM compiler backends and/or MLIR.

Ph.D. or advanced research experience in computer architecture, compilers, or HPC.