Solutions Manager - Silicon Platform Validation, Python

Chennai, Tamil Nadu

Job Summary

This role is responsible for driving the architecture, design, and delivery of RTL solutions for complex digital systems. The individual provides expert technical leadership, ensures adoption of advanced methodologies, and guides team members in delivering high-quality, scalable, and innovative solutions aligned with client and organizational objectives.

Key Responsibilities

1. Architect RTL-based solutions using Verilog/SystemVerilog, defining module specifications and design methodologies to achieve project requirements and industry standards.

2. Design and implement RTL logic for high-performance digital circuits using EDA tools such as Synopsys Design Compiler and Cadence Genus, ensuring functional correctness and timing closure.

3. Oversee team development activities in RTL coding, simulation, and synthesis, providing expert guidance and resolving technical challenges.

4. Act as a subject matter expert on RTL design, supporting the adoption of new technologies and driving continuous improvement initiatives within the team.

5. Review and validate RTL deliverables using formal verification tools including Mentor Questa and JasperGold, ensuring compliance with client specifications and quality benchmarks.

6. Lead knowledge enhancement activities by mentoring team members in advanced RTL design concepts, tool usage, and best practices to maintain a high skill level within the group.

7. Collaborate with internal stakeholders to gather domain-specific requirements and translate them into innovative RTL architectures and solutions.

8. Recommend and implement industry best practices in RTL design, identifying opportunities for client value creation and technology optimization.

Skill Requirements

1. Expert proficiency in RTL Design using Verilog/SystemVerilog, demonstrating architectural leadership and strategic thinking in digital system development.

2. Excellent knowledge of EDA tools such as Synopsys Design Compiler, Cadence Genus, and Mentor Questa for synthesis, simulation, and verification.

3. Advanced understanding of digital design principles, timing analysis, and low-power techniques.

4. Solid expertise in formal verification methodologies and tools for RTL validation.

5. Strong skills in technical leadership, mentoring, and team development within RTL design projects.

6. In-depth familiarity with industry standards such as IEEE and experience in applying best practices for quality and scalability.

Other Requirements

1. Recommended: Synopsys Certified Professional – Design & Verification (optional but valuable)

2. Recommended: Cadence Certified RTL Designer (optional but valuable)

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